The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a micropattern of a semiconductor device.
As the integration density of semiconductor devices increases, sub-40 nm line and space (LS) is required. However, due to the limitation of existing exposure apparatuses, it is difficult to form sub-60 nm LS.
In order to form sub-60 nm LS while using existing exposure apparatuses, a double patterning technology (DPT) and a spacer patterning technology (SPT) have been proposed.
FIG. 1 illustrates a cross-sectional view of a micropattern of a semiconductor device fabricated by an SPT process. The SPT process fabricates two lines (L) and two spacers (S) within 1 pitch, thus increasing the integration degree of a cell. Although the SPT process can provide two times the integration degree of the cell compared with the typical technology, a new fabrication process is required to further increase the integration degree of the cell.
Furthermore, the semiconductor device includes an etch target layer (a lower structure) 100, a hard mask 101, spacers 102 serving as a pattern mask, and a sacrificial layer 103.